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KS88C2064 product o verview 1- 1 1 product overview ks88-series microcontrollers samsung?s ks88 series of 8-bit single-chip cmos microcontrollers offers a fast and efficient cpu, a wide range of integrated peripherals, and various mask-programmable rom sizes. important cpu features include: ? efficient register-oriented architecture ? selectable cpu clock sources ? idle and stop power-down mode release by interrupt ? built-in basic timer with watchdog function a sophisticated interrupt structure recognizes up to eight interrupt levels. each level can have one or more interrupt sources and vectors. fast interrupt processing (within a minimum six cpu clocks) can be assigned to specific interrupt levels. KS88C2064 microcontroller the KS88C2064 single-chip cmos microcontroller is fabricated using a highly advanced cmos process and is based on samsung?s newest cpu architecture. the KS88C2064 is the microcontroller which has 64-kbyte mask-programmable rom and 192-kbyte mask rom for font data. using a proven modular design approach, samsung engineers developed the KS88C2064 by integrating the following peripheral modules with the powerful sam87 core: ? four programmable i/o ports, excluding one buz pin, for a total of 32 pins. ? eight bit-programmable pins for external interrupts. ? one 8-bit b asic timer for oscillation stabilization and watchdog functions (system reset). ? one 8-bit timer/counter and one 16-bit timer/counter with selectable operating modes. ? watch timer for real time. the KS88C2064 is a versatile microcontroller for data bank or dictionary. it is currently available in a 128-pin qfp package.
product overview ks 88c2064 1- 2 features cpu ? sam87 cpu core memory ? 64-kbyte internal program memory (rom) ? 192-kbyte internal memory (rom) for font data ? 272-byte internal register file (excluding lcd ram) ? 6144-b yte data ram instruction set ? 78 instructions ? idle and stop instructions added for power-down modes instruction execution time ? 1.5 m s at 4 mhz fx (minimum) ? 183 m s at 32,768 hz fxt interrupts ? five interrupt levels and 15 interrupt sources ? 15 vectors (15 sources have a dedicated vector address) ? fast interrupt processing feature (for one selected interrupt level) i/o ports ? four 8-bit i/o ports (p0?p3) for a total of 32-bit programmable pins ? eight input pins for external interrupts ? one output only pin for buz watch timer ? interval time: 3.91 ms, 1s at 32,768 hz ? four frequency outputs to buz pin and buz pin ? clock source generation for lcd lcd controller/driver ? 65 segments and 18 common terminals ? internal resistor circuit for lcd bias ? voltage doubler ? all dot can be switched on/off timers and timer/counters ? one programmable 8-bit basic timer (bt) for oscillation stabilization control or watchdog timer (software reset) function ? one 8-bit timer/counter (timer 0) with three operating modes; interval, capture and pwm ? one 16-bit timer/counter (timer 1) with two 8- bit timer/counter modes; interval power-down modes ? idle mode (cpu clock stops) ? stop mode (main oscillation and cpu clock stops) operating temperature range ? ? 40 c to + 85 c operating voltage range ? 2.2 v to 4.5 v at 1 mhz fx ? 2.7 v to 4.5 v at 4 mhz fx package type ? 128-pin qfp
KS88C2064 product o verview 1- 3 block diagram watch timer 64-kbyte rom i/o port and interrupt control sam8 cpu port 0 314-byte register file internal bus port 1 192-kbyte font rom 6144-byte data ram basic timer main osc sub osc timer 0 x in x out xt in xt out buz buz t0 t0ck reset port 2 port 3 timer 1 lcd driver/ controller voltage doubler test p2.0-p2.3 ( as, dw, dr, dm ) p2.4-p2.7 (t0, t0ck, clo, buz) p3.0/tb/int0 p3.1/ta/int1 p3.2/t1ck/int2 p3.3/int3 p3.4/int4 p3.5/int5 p3.6/int6 p3.7/int7 com0-com8 com9-com17 seg0-seg64 v lc0 bias ca cb ta tb t1ck p0.0-p0.7 (a8-a15) p1.0-p1.7 (ad0-ad7) figure 1-1. block diagram
product overview ks 88c2064 1- 4 pin assignments seg36 seg37 seg38 seg39 seg40 seg41 seg42 seg43 seg44 seg45 seg46 seg47 seg48 seg49 seg50 seg51 seg52 seg53 seg54 seg55 seg56 seg57 seg58 seg59 seg60 seg61 seg62 seg63 seg64 com0 com1 com2 com3 com4 com5 com6 com7 com8 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com9 com10 com11 com12 com13 com14 com15 com16 com17 v dd v ss x out x in test xt in xt out reset p0.7/a15 p0.6/a14 p0.5/a13 p0.4/a12 p0.3/a11 p0.2/a10 p0.1/a9 p0.0/a8 p1.7/ad7 p1.6/ad6 p1.5/ad5 KS88C2064 (128-qfp-1420) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 p1.4/ad4 p1.3/ad3 p1.2/ad2 p1.1/ad1 p1.0/ad0 p3.0/tb/int0 p3.1/ta/int1 p3.2/t1ck/int2 p3.3/int3 p3.4/int4 p3.5/int5 p3.6/int6 p3.7/int7 p2.0/ as p2.1/ dw p2.2/ dr p2.3/ dm p2.4/t0 p2.5/t0ck p2.6/clo p2.7/buz buz ca cb v lc0 bias seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32 seg33 seg34 seg35 figure 1-2. pin assignment (128-pin qfp package)
KS88C2064 product o verview 1- 5 pin descriptions table 1-1. pin descriptions pin names pin type pin description circuit type pin no. shared functions p0.0?p0.7 i/o i/o port with nibble-programmable pins; schmitt trigger input or push-pull, open-drain output and software assignable pull-up; also configurable as external interface address lines a8 ?a15. 3 35?28 a8?a15 p1.0?p1.7 i/o same general characteristics as port 0; also configurable as external interface address/data lines ad0?ad7. 3 43?36 ad0?ad7 p2.0?p2.3 i/o i/o port with bit-programmable pins; schmitt trigger input or push-pull output and software assignable pull-ups. lower nibble pins 0?3 are configurable for external interface signals. 5 52?55 as , dw , dr , dm p2.4?p2.7 i/o p2.4/capture input, interval/pwm output (t0) p2.5/timer 0 clock input (t0ck) p2.6/system clock output (clo) p2.7/buzzer signal output (buz) 6 56?59 t0, t0ck, clo, buz p3.0?p3.7 i/o i/o port with bit-programmable pins; schmitt trigger input or push-pull output and software assignable pull-up; p3.0?p3.7 are alternately used for external interrupt input (noise filters, interrupt enable and pending control); p3.0/timer b clock output (tb)/int0 p3.1/timer 1/a clock output (ta)/int1 p3.2/timer 1/a clock input (t1ck)/int2 4 44?51 tb/int0, ta/int1, t1ck/int2, int3?int7 t1ck i/o timer a external clock input pins. 4 46 p3.2/int2 tb ta i/o timer b and 1/a clock output pins. 4 44 45 p3.0/int0 p3.1/int1 as , dw , dr , dm i/o output pins for external interface control signals. as : address strobe dw : data memory write dr : data memory read dm : data memory select 5 52?55 p2.0?p2.3 t0 i/o capture input or interval/pwm output. 6 56 p2.4 t0ck i/o timer 0 clock input. 6 57 p2.5
product overview ks 88c2064 1- 6 table 1-1. pin descriptions (continued) pin names pin type pin description circuit type pin no. shared functions clo i/o clock output 6 58 p2.6 buz i/o output pin for buzzer signal. 6 59 p2.7 buz o inverted buzzer signal output. ? 60 ? int0?int7 i/o external interrupt input pins. 4 44?51 p3.0/tb, p3.1/ta, p3.2/t1ck, p3.3?p3.7 ad0?ad7 i/o address low and data ports. 3 43?36 p1.0?p1.7 a8?a15 i/o address high output ports. 3 35?28 p0.0?p0.7 com0?com8 o lcd common signal output. 7 73?65 ? com9? com17 o lcd common signal output. 7 11?19 ? seg0? seg64 o lcd seg signal output. 8 10?1 128?74 ? ca, cb ? capacitor terminal for voltage doubling. ? 61, 62 ? v lc0 ? lcd power supply. ? 63 ? bias o bias voltage level for lcd driving. ? 64 ? reset i system reset pin 2 27 ? xt in , xt out ? crystal oscillator pins for sub clock. ? 25, 26 ? test i test signal input (must be connected to v dd ). ? 24 ? x in , x out ? main oscillator pins ? 23, 22 ? v dd , v ss ? power input pins ? 20, 21 ?
KS88C2064 product o verview 1- 7 pin circuit diagrams p-channel n-channel in v dd figure 1-3. pin circuit type 1 in v dd pull-up resistor schmitt trigger figure 1-4. pin circuit type 2 ( reset ) i/o pull-up enable v dd pull-up resistor v dd v ss data open-drain output disable input figure 1-5. pin circuit type 3 (ports 0, 1)
product overview ks 88c2064 1- 8 pin circuit diagrams (c ontinued ) i/o pull-up enable v dd pull-up resistor v dd v ss output disable data external interrupt input noise filter input figure 1-6. pin circuit type 4 (port 3)
KS88C2064 product o verview 1- 9 pin circuit diagrams (c ontinued ) i/o pull-up enable v dd pull-up resistor v dd v ss output disable input data m u x select port 2 (low byte) data external interface ( as, dw, dr, dm ) figure 1-7. pin circuit type 5 (ports 2.0?2.3) i/o pull-up enable v dd pull-up resistor v dd v ss output disable input data figure 1-8. pin circuit type 6 (ports 2.4?2.7)
product overview ks 88c2064 1- 10 pin circuit diagrams (c ontinued ) out v lc0 v lc1 com v lc4 v ss figure 1-9. pin circuit type 7 ( com0 ? com17) out v lc0 v lc2 seg v lc3 v ss figure 1-10. pin circuit type 8 (seg0?seg64)
KS88C2064 electrical data 1 5 - 1 1 5 electrical data overview in this chapter, KS88C2064 electrical characteristics are presented in tables and graphs. the information is arranged in the following order: ? absolute maximum ratings ? d.c. electrical characteristics ? data retention supply voltage in stop mode ? stop mode release timing when initiated by an external interrupt ? stop mode release timing when initiated by a reset ? i/o capacitance ? a.c. electrical characteristics ? input timing for external interrupts (port 0, p2.3?p2.0) ? input timing for reset ? oscillation characteristics ? oscillation stabilization time
electrical data KS88C2064 15 - 2 table 15- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd ? ? 0.3 to + 5.5 v input voltage v in ports 0, 1, 2, and 3 ? 0.3 to v dd + 0.3 v output voltage v o all output pins ? 0.3 to v dd + 0.3 v output current high i oh one i/o pin active ? 18 ma all i/o pins active ? 60 output current low i ol one i/o pin active + 30 ma total pin current for ports 0 ?3 + 100 operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c
KS88C2064 electrical data 1 5 - 3 table 15- 2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.2 v to 4.5 v) parameter symbol conditions min typ max unit input high voltage v ih1 all input pins except v ih2 and v ih3 0.8 v dd ? v dd v v ih2 reset 0.8 v dd v dd v ih3 x in , x t in v dd ? 0.5 v dd input low voltage v il1 all input pins except v il2 and v il3 0 ? 0.2 v dd v il2 reset 0.2 v dd v il3 x out , x t out 0.5 output high voltage v oh v dd = 3.0 v; i oh = ? 1 ma all output pins v dd ? 1.0 ? ? output low voltage v ol v dd = 3.0 v; i o l = 2 ma all output pins ? ? 1.0 input high leakage current i lih1 v in = v dd ; all input pins except x in , x out , xt in , and xt out ? ? 1 a i lih2 v in = v dd ; x in , x out , xt in , and xt out 20 input low leakage current i lil1 v in = 0 v; all input pins except x in , x out , xt in , and xt out ? ? ? 1 i lil2 v in = 0 v ; x in , x out , xt in , and xt out ? 20 output high leakage current i loh v out = v dd all output pins ? ? 1 output low leakage current i lol v out = 0 v all output pins ? ? ? 1
electrical data KS88C2064 15 - 4 table 15- 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.2 v to 4.5 v) parameter symbol conditions min typ max unit middle output v om1 v mn = v lcd ? (n/5) com0?17 v m1 ? 0.2 v m1 v m1 + 0.2 v voltage v om2 v lcd seg0?64 v m2 ? 0.2 v m2 v m2 + 0.2 v om3 n = 1, 2, 3, and 4 seg0?64 v m3 ? 0.2 v m3 v m3 + 0.2 v om4 com0?17 v m4 ? 0.2 v m4 v m4 + 0.2 | v lcd ?v comi | voltage drop ( i = 0?17) v dc v lcd = 3.0 v to 6.0 v ? 15 m a per common pin ? ? 120 mv | v lcd ?v segx | voltage drop (x = 0?64) v ds v lcd = 3.0 v to 6.0 v ? 15 m a per common pin ? ? 120 mv lcd driving voltage v lcd ? 3.0 ? 6.0 v pull-up resistors r l1 v in = 0 v; t a = 25 c; v dd = 3.0 ports 0, 1, 2, and 3 30 80 200 k w r l2 v in = 0 v; t a = 25 c; v dd = 3.0 reset only 300 500 800 lcd voltage dividing resistor r lcd v lcd = 3.0 v to 6.0 v t a = 25 c 40 60 80 k w supply current ( n ote) i dd1 v dd = 3 .0 v 10% 2 mhz crystal ? 1.5 3.5 ma i dd2 idle mode; v dd = 3 .0 v 10% 2 m hz crystal 0.5 1.5 i dd 3 v dd = 3 .0 v 10% 32 k hz crystal 30 70 a i dd 4 idle mode; v dd = 3 .0 v 10% 32 k hz crystal 6 12 i dd 5 stop mode; v dd = 3 .0 v 10% xt in = 0 v 0.5 1 note s : 1. supply current does not include current drawn through internal pull-up resistors , lcd voltage dividing resistors, voltage doubler, or external output current loads. 2. i dd1 and i dd2 include power consumption for subsystem clock oscillation. 3. i dd3 and i dd4 are current when main system clock oscillation stops and the subsystem clock is used.
KS88C2064 electrical data 1 5 - 5 table 15- 3. data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 2.2 ? 4.5 v data retention supply current i dddr v dddr = 2.2 v ? ? 5 a release signal set time t srel ? 0 ? ? s oscillator stabilization t wait released by reset ? 2 16 / fx (1) ? ms wait time released by interrupt ? (2) ? notes: 1. fx is the main oscillator frequency. 2. the duration of the oscillation stabilization time (t wait ) when it is released by an interrupt is determined by the setting in the basic timer control register, btcon. execution of stop instrction v dddr ~ ~ data retention mode v dd normal operating mode ~ ~ stop mode idle mode (basic timer active) t wait interrupt request 0.8 v dd figure 15- 1. stop mode release timing when initiated by a n external interrupt
electrical data KS88C2064 15 - 6 normal operating mode execution of stop instrction reset occurs ~ ~ v dddr ~ ~ stop mode oscillation stabilization time data retention mode t wait reset v dd 0.2 v dd 0.8 v dd t srl figure 15-2 . stop mode release timing when initiated by a reset
KS88C2064 electrical data 1 5 - 7 table 15-4. input/output capacitance (t a = ? 40 c to + 85 c, v dd = 0 v) parameter symbol conditions min typ max unit input capacitance c in f = 1 mhz; unmeasured pins are connected to v ss ? ? 10 pf output capacitance c out i/o capacitance c io table 15- 5. a.c. electrical characteristics (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit interrupt input, high, low width t int h , t int l p 3.0?p3.7 v dd = 3 v 500 700 ? ns reset input low width t rsl input v dd = 3 v 20 00 ? ? table 15-6 . voltage doubler output (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit voltage doubler output v bias v dd = 3 v 10 % only 2 v dd ? 0.5 2 v dd 2 v dd + 0.5 v t inth t intl 0.8 v dd 0.2 v dd note: the unit t cpu means one cpu clock period. figure 15-3 . input timing for external interrupts (p3.0?p3.7)
electrical data KS88C2064 15 - 8 reset t rsl 0.3 v dd figure 15-4 . input timing for reset table 15-7 . main osc illation characteristics (t a = ? 40 c + 85 c , v dd = 2.2 v to 4.5 v ) oscillator clock circuit conditions min typ max unit crystal x in c1 c2 x out cpu clock oscillation frequency 0.4 ? 4 mhz ceramic x in c1 c2 x out cpu clock oscillation frequency 0.4 ? 4 mhz external clock x in x out x in input frequency 0.4 ? 4 mhz rc x in x out frequency, v dd = 3 v 0.4 ? 2 mhz
KS88C2064 electrical data 1 5 - 9 table 15-8 . sub oscillation characteristics (t a = ? 40 c + 85 c , v dd = 2.2 v to 4.5 v ) oscillator clock circuit conditions min typ max unit crystal x in c1 c2 x out cpu clock oscillation frequency 32 32.768 35 k hz external clock x in x out xt in input frequency 32 ? 500 k hz table 15-9 . main oscillation stabilization time (t a = ? 40 c + 85 c, v dd = 3.0 v 10 % ) oscillator test condition min typ max unit c rystal f x > 400 khz ? ? 80 ms c eramic oscillation stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 5 0 ms external clock x in input high and low width (t xh , t xl ) 25 ? 700 ns x in t xh t xl 1/fx v dd - 0.5 v 0.5 v figure 15-5. clock timing measurement at x in
electrical data KS88C2064 15 - 10 table 15-10 . sub oscillation stabilization time (t a = ? 40 c + 85 c, v dd = 3.0 v 10 % ) oscillator test condition min typ max unit c rystal ? ? 1.0 2 s external clock x in input high and low width (t xh , t xl ) 1 ? 18 m s xt in t xth t xtl 1/fxt v dd - 0.5 v 0.5 v figure 15-6. clock timing measurement at xt in
KS88C2064 electrical data 1 5 - 11 666 khz instruction clock 8.32 khz 2 5 167 khz 333 khz 3 4 supply voltage (v) instruction clock = 1/6n x oscillator frequency ( n = 1, 2, 8, 16) 2.2 2.7 2.4 4.5 1 mhz 2 mhz 4 mhz 400 khz fx (main oscillation frequency) figure 15-7. operating voltage range
KS88C2064 mechanical data 16 - 1 1 6 mechanical data overview the KS88C2064 micr ocontroller is currently available in a 128 -pin tqfp package. 128-qfp-1420 #128 20.00 0.20 22.00 0.30 14.00 0.20 16.00 0.30 0.15 + 0.10 - 0.05 0-8 0.10 max #1 note : dimensions are in millimeters. (0.75) 0.50 0.20 0.05 min 2.10 0.10 2.40 max 0.50 0.20 0.50 0.20 + 0.10 - 0.05 (0.75) 0.10 max 0.10 max figure 16-1. 128- pin tqf p package mechanical data

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